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arXiv:1607.02318cs.AR

The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V

Christopher Celio, Palmer Dabbelt, David A. Patterson, Krste Asanović

Abstract

This report makes the case that a well-designed Reduced Instruction Set Computer (RISC) can match, and even exceed, the performance and code density of existing commercial Complex Instruction Set Computers (CISC) while maintaining the simplicity and cost-effectiveness that underpins the original RISC goals. We begin by comparing the dynamic instruction counts and dynamic instruction bytes fetched for the popular proprietary ARMv7, ARMv8, IA-32, and x86-64 Instruction Set Architectures (ISAs) against the free and open RISC-V RV64G and RV64GC ISAs when running the SPEC CINT2006 benchmark suite. RISC-V was designed as a very small ISA to support a wide range of implementations, and has a less mature compiler toolchain. However, we observe that on SPEC CINT2006 RV64G executes on average 16% more instructions than x86-64, 3% more instructions than IA-32, 9% more instructions than ARMv8, but 4% fewer instructions than ARMv7. CISC x86 implementations break up complex instructions into smaller internal RISC-like micro-ops, and the RV64G instruction count is within 2% of the x86-64 retired micro-op count. RV64GC, the compressed variant of RV64G, is the densest ISA studied, fetching 8% fewer dynamic instruction bytes than x86-64. We observed that much of the increased RISC-V instruction count is due to a small set of common multi-instruction idioms. Exploiting this fact, the RV64G and RV64GC effective instruction count can be reduced by 5.4% on average by leveraging macro-op fusion. Combining the compressed RISC-V ISA extension with macro-op fusion provides both the densest ISA and the fewest dynamic operations retired per program, reducing the motivation to add more instructions to the ISA. This approach retains a single simple ISA suitable for both low-end and high-end implementations, where high-end implementations can boost performance through microarchitectural techniques.

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Subjects
cs.ARHardware Architecture

On Hacker News

Linked by 9 identifiable commenters in 14 comments across 11 threads, from Jul 2016 to Jan 2025. Found in 1 HN submission from Sep 2016 to Sep 2016. Open submission discussions.

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Discussed in comments11 threads

  1. XiangShan – Open-source high performance RISC-V processor 1 comment

    • The ISA spec itself suggests one fusion - that of mul and mulh (lower and upper halves of n-bit * n-bit -> 2n-bit product). The only other source I know of was this 2016 paper that suggested specific macro fusions. https://arxiv.org/abs/1607.02318 This predates the B extension…

      ArnavionView on HNParent context

  2. ARM: Pragmatism, Not Purity 1 comment

    • https://arxiv.org/abs/1607.02318 is a widely cited paper that argues that simple and orthogonal ISA's are preferable, as fusion can fix up those common cases like more complicated addressing modes that other ISA's have in the base ISA.

      jablView on HNParent context

  3. India reveals RISC-V CPU roadmap, expects product by 2023 1 comment

    • Hmm, not even the Allwinner D1 or the SiFive P650? In https://news.ycombinator.com/item?id=29423006 Bruce Hoult says SiFive has been doing macro-op fusion in one case since the 7-series, and I think he's the one that implemented it. In…

      kragenView on HNParent context

  4. RISC-V is succeeding 1 comment

    • That's true if you take the strict textbook definition of "RISC" and "CISC" but everyone has been saying for 10+ years that really isn't how things work anymore. ARM has pulled a lot of the "useful goodies" out of CISC ISAs and CISC ISAs have gone to RISC micro-ops internally on…

      paulmdView on HNParent context

  5. Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor 1 comment

    • I don't know why you're being downvoted, because you are correct. It's an explicit goal of RISC-V to support complex operations by using a mixture of macro-op fusion and extensions, rather than trying to encode everything in the base architecture. Source for macro-op fusion…

      rwmjView on HNParent context

  6. Boom v2: Open-source out-of-order RISC-V core [video] 2 comments

    • FWIW, the paper, with more details than the slides, is https://arxiv.org/abs/1607.02318

      jablView on HNParent context

    • Risc-V, 64 bit w/ compressed instructions (strict subset of 32 bit instrs, freely intermix-able) is beating x86_64 right now in static and dynamic code size without vector extensions or anything fancy. With a few simple macro-op fusion pairs, it also comes right up to x86_64 in…

      baobrienView on HNParent context

  7. Power9 to the People 1 comment

    • I guess the "even more important" thing you're thinking of is https://arxiv.org/abs/1607.02318 ? So with RISC-V GC + macro fusion of a few common idioms you get slightly less micro-ops than x86-64, armv7, or armv8. That being said, for high-performance cores such as Skylake…

      jablView on HNParent context

  8. BOOM v2: an open-source out-of-order RISC-V core 3 comments

    • > Chris, I worked hard to get you on that pedestal, don't go jumping off. ;- ) O:-) > ARM[v7] maybe does a little bit more per instruction, what with those conditions and 14+ character non-mnemonic mnemonics; but ultimately instruction counts should be pretty close, right? Great…

      _chris_View on HNParent context

    • The ISA is going to have close to zero impact on a processor's performance. I actually wrote up another tech report on this topic (https://arxiv.org/abs/1607.02318). In short, you can rely on macro-op fusion to dynamically fuse some idioms that show up as instructions in other…

      _chris_View on HNParent context

    • > Great question. I just so happen to have written a tech report on this very topic! https://arxiv.org/abs/1607.02318 . > Basically, performance should be identical between ARMv8 and RISC-V, given the RISC-V core implements macro-op fusion to combine things like pair loads…

      microcolonelView on HNParent context

  9. Ask HN: What's the value proposition of RISC-V? 1 comment

    • I'd like to know what the problem was with ARM's ISA that presented problems for superscalar. Load/store multiple, for starters. Even just load-pair-increment-address is a pain as it requires 3 write ports. https://arxiv.org/pdf/1607.02318.pdf

      _chris_View on HNParent context

  10. LowRISC – An open-source, Linux-capable System-on-a-Chip 1 comment

    • Performance solely depends on the design team and their market targets, not the ISA (https://arxiv.org/abs/1607.02318).

      _chris_View on HNParent context

  11. Show HN: Accelerating SHA256 by 100x in Golang on ARM 1 comment

    • I think RISC-V is showing that RISC ISAs can still compete in this space: https://arxiv.org/pdf/1607.02318v1.pdf. RISC-V has extensibility of the ISA as a core feature, allowing for special-purpose accelerators and coprocessors as needed.

      cmrx64View on HNParent context

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