The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V · HackerPapers discussions

The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V — mentioned by Arnavion

Fri, 03 Jan 2025 18:50:05 GMT

The ISA spec itself suggests one fusion - that of mul and mulh (lower and upper halves of n-bit * n-bit -> 2n-bit product). The only other source I know of was this 2016 paper that suggested specific macro fusions. https://arxiv.org/abs/1607.02318 This predates the B extension so some of those fusions are dedicated instructions now, but I suppose Xiangshan still implements them for the sake of software that was not compiled with B enabled.

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V — mentioned by jabl

Tue, 15 Nov 2022 15:45:52 GMT

https://arxiv.org/abs/1607.02318 is a widely cited paper that argues that simple and orthogonal ISA's are preferable, as fusion can fix up those common cases like more complicated addressing modes that other ISA's have in the base ISA.

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V — mentioned by kragen

Tue, 03 May 2022 10:48:19 GMT

Hmm, not even the Allwinner D1 or the SiFive P650? In https://news.ycombinator.com/item?id=29423006 Bruce Hoult says SiFive has been doing macro-op fusion in one case since the 7-series, and I think he's the one that implemented it. In https://news.ycombinator.com/item?id=29444322 "ruslan" links the original macro-op fusion stuff from 02016: https://riscv.org/wp-content/uploads/2016/07/Tue1130celio-fu... and https://arxiv.org/abs/1607.02318. Surprisingly, those present "shootout" results that are really just "effective dynamic instruction" counts and "dynamic byte" counts, ending in a "design…

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V — mentioned by paulmd

Tue, 01 Mar 2022 21:09:52 GMT

That's true if you take the strict textbook definition of "RISC" and "CISC" but everyone has been saying for 10+ years that really isn't how things work anymore. ARM has pulled a lot of the "useful goodies" out of CISC ISAs and CISC ISAs have gone to RISC micro-ops internally on a lot of things. And x86-64 is really not all that dense anyway either. Also, a huge amount of instructions end up being used very little, there are a few "hotspot" instructions that make up a huge percent of actual instructions executed. https://arxiv.org/pdf/1607.02318.pdf Measured code density on SPEC2006, ARMv8…

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V — mentioned by rwmj

Sat, 08 Jun 2019 08:36:37 GMT

I don't know why you're being downvoted, because you are correct. It's an explicit goal of RISC-V to support complex operations by using a mixture of macro-op fusion and extensions, rather than trying to encode everything in the base architecture. Source for macro-op fusion claim: Celio, Christopher, et al. "The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V." arXiv preprint arXiv:1607.02318 (2016). Source for extension claim: https://en.wikipedia.org/wiki/RISC-V#ISA_base_and_extensions (Note "B" extension for bit ops)

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V — mentioned by baobrien

Sun, 10 Dec 2017 23:30:29 GMT

Risc-V, 64 bit w/ compressed instructions (strict subset of 32 bit instrs, freely intermix-able) is beating x86_64 right now in static and dynamic code size without vector extensions or anything fancy. With a few simple macro-op fusion pairs, it also comes right up to x86_64 in dynamic uOp count. https://arxiv.org/pdf/1607.02318.pdf

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V — mentioned by jabl

Sun, 10 Dec 2017 19:01:40 GMT

FWIW, the paper, with more details than the slides, is https://arxiv.org/abs/1607.02318

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V — mentioned by jabl

Wed, 06 Dec 2017 13:02:18 GMT

I guess the "even more important" thing you're thinking of is https://arxiv.org/abs/1607.02318 ? So with RISC-V GC + macro fusion of a few common idioms you get slightly less micro-ops than x86-64, armv7, or armv8. That being said, for high-performance cores such as Skylake, POWER9, or the latest aarch64 server cores the ISA probably doesn't matter that much.

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V — mentioned by microcolonel

Wed, 27 Sep 2017 04:52:26 GMT

> Great question. I just so happen to have written a tech report on this very topic! https://arxiv.org/abs/1607.02318 . > Basically, performance should be identical between ARMv8 and RISC-V, given the RISC-V core implements macro-op fusion to combine things like pair loads together. Yeah, I drew my conclusions from your papers. :- ) I really should diversify my sources, I bring nothing to this exchange.

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V — mentioned by _chris_

Wed, 27 Sep 2017 02:05:44 GMT

The ISA is going to have close to zero impact on a processor's performance. I actually wrote up another tech report on this topic (https://arxiv.org/abs/1607.02318). In short, you can rely on macro-op fusion to dynamically fuse some idioms that show up as instructions in other ISAs, like load-pair.

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V — mentioned by _chris_

Wed, 27 Sep 2017 01:34:30 GMT

> Chris, I worked hard to get you on that pedestal, don't go jumping off. ;- ) O:-) > ARM[v7] maybe does a little bit more per instruction, what with those conditions and 14+ character non-mnemonic mnemonics; but ultimately instruction counts should be pretty close, right? Great question. I just so happen to have written a tech report on this very topic! https://arxiv.org/abs/1607.02318 Basically, performance should be identical between ARMv8 and RISC-V, given the RISC-V core implements macro-op fusion to combine things like pair loads together.

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V — mentioned by _chris_

Wed, 21 Dec 2016 01:29:11 GMT

I'd like to know what the problem was with ARM's ISA that presented problems for superscalar. Load/store multiple, for starters. Even just load-pair-increment-address is a pain as it requires 3 write ports. https://arxiv.org/pdf/1607.02318.pdf

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V — mentioned by _chris_

Thu, 08 Dec 2016 12:24:33 GMT

Performance solely depends on the design team and their market targets, not the ISA (https://arxiv.org/abs/1607.02318).

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V — HN submission

Mon, 26 Sep 2016 14:50:29 GMT

Avoiding ISA Bloat with Macro-Op Fusion for RISC-V

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The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V — mentioned by cmrx64

Thu, 28 Jul 2016 08:36:24 GMT

I think RISC-V is showing that RISC ISAs can still compete in this space: https://arxiv.org/pdf/1607.02318v1.pdf. RISC-V has extensibility of the ISA as a core feature, allowing for special-purpose accelerators and coprocessors as needed.

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