Scaling Two-Dimensional Semiconductor Nanoribbons for High-Performance Electronics

Abstract

As silicon transistors scale toward future technology nodes, three-dimensional architectures -- including gate-all-around (GAA) nanoribbon and complementary field-effect transistors (CFETs) -- require channel widths in the tens of nanometers to meet density targets. Monolayer transition metal dichalcogenides (TMDs), with their atomically thin bodies, are promising channel materials for these architectures, yet most TMD-based FETs remain limited to micrometer-scale widths. Here, we show that channel width scaling of monolayer MoS2 nanoribbon transistors not only preserves but also enhances device performance. Reducing the channel width from hundreds of nanometers to $\sim$30--40 nm increases the median on-current density by $\sim$42% and reduces the median subthreshold swing by $\sim$16%, with a champion device reaching 995 $μ$A $μ$m$^{-1}$ at a drain-to-source voltage of 1 V and an overdrive voltage of 2.5 V. We attribute these improvements to three mechanisms: minimal edge-induced disorder, enhanced gate electrostatics at ribbon edges, and more efficient side-contact injection, together reducing contact resistance from $\sim$860 $Ω$ $μ$m to $\sim$270 $Ω$ $μ$m. Extending the platform to n-type WS2 and p-type WSe2 FETs, we achieve WSe2 p-FET on-currents of 357 $μ$A $μ$m$^{-1}$. These findings suggest that monolayer TMD nanoribbon FETs are promising candidates for future ultra-scaled electronics.