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<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Flexing RISC-V Instruction Subset Processors to Extreme Edge · HackerPapers discussions</title><link>https://hackerpaper.kaipfister.de/p/2505.04567/</link><description>Collected HN comments and submissions linking this paper.</description><language>en</language><lastBuildDate>Mon, 02 Nov 2026 11:27:26 GMT</lastBuildDate><atom:link href="https://hackerpaper.kaipfister.de/p/2505.04567/feed.xml" rel="self" type="application/rss+xml" /><item><title>Flexing RISC-V Instruction Subset Processors to Extreme Edge — HN submission</title><link>https://news.ycombinator.com/item?id=44115240</link><guid isPermaLink="false">urn:hackerpapers:submission:2505.04567:44115240</guid><pubDate>Wed, 28 May 2025 12:21:28 GMT</pubDate><description>&lt;p&gt;Flexing RISC-V Instruction Subset Processors (RISPs) to Extreme Edge&lt;/p&gt;&lt;p&gt;&lt;/p&gt;&lt;p&gt;4 points; 2 discussion replies on HN. &lt;a href="https://hackerpaper.kaipfister.de/p/2505.04567/"&gt;Paper and source history&lt;/a&gt;. A submission is not an endorsement.&lt;/p&gt;</description><category>cs.AR</category></item></channel></rss>
