arXiv:2503.19544physics.optics
Design of Energy-Efficient Cross-coupled Differential Photonic-SRAM (pSRAM) Bitcell for High-Speed On-Chip Photonic Memory and Compute Systems
Abstract
In this work, we propose a novel differential photonic static random access memory (pSRAM) bitcell design using fabrication-friendly photonic components. The proposed pSRAM overcomes the key limitations of traditional electrical SRAMs, which struggle with speed and power efficiency due to increasing bitline/wordline capacitance and interconnect resistance associated with long electrical wires as technology scales. By utilizing cross-coupled micro-ring resonators and differential photodiode structures, along with optical waveguides instead of traditional wordlines and bitlines, our pSRAM exhibits high-speed, and energy-efficient performance. The pSRAM bitcell demonstrates a read/write speed of 40 GHz, with a switching (static) energy consumption of approximately 0.6 pJ (0.03 pJ) per bit and a footprint of 330x290 um^2 using the GlobalFoundries 45SPCLO process node. These bitcells can be arranged into a 2D memory array, enabling large-scale, on-chip photonic memory subsystems ideal for high-speed memory, data processing and computing applications.
From the paper > footprint of 330 × 290 µm2 using the GlobalFoundries 45SPCLO That’s a 45nm process but the units for the chip size probably should have been 330um? However I’m not well versed enough in the details to parse it out. https://arxiv.org/abs/2503.19544
vlovich123View on HNParent context
Free version of the research paper: https://arxiv.org/abs/2503.19544v1 The memory cell is huge in comparison with semiconductor memories, but it is very fast, with a 40 GHz read/write speed. There are important applications for a very high speed small memory, e.g. for digital…
adrian_bView on HNParent context