Instruction Scheduling in the Saturn Vector Unit — mentioned by camel-cdr

Tue, 10 Dec 2024 10:22:25 GMT

"Short reasons for long vectors in HPC CPUs: a study based on RISC-V": https://arxiv.org/abs/2309.06865 Suggests that VLEN>DLEN can help hide the memory latency. "Instruction Scheduling in the Saturn Vector Unit": https://arxiv.org/html/2412.00997v1 > VII-A Chime Length > The “native” chime length in Saturn, for instructions with no register grouping, is given by the VLEN:DLEN ratio. Increasing the native chime length reduces overall throughput pressure on many components in Saturn, including instruction fetch, load-store queue sizes, issue-queue sizes, and sequencer throughput. > However, a…

Paper and discussion history. A mention is not an endorsement.

Instruction Scheduling in the Saturn Vector Unit · HackerPapers discussions

Instruction Scheduling in the Saturn Vector Unit — mentioned by camel-cdr