VerilogEval: Evaluating Large Language Models for Verilog Code Generation — mentioned by pbazarnik

Wed, 08 Nov 2023 06:28:08 GMT

It looks like availability of good quality training sets will be a stumbling block for LLM use in Verilog chip design since pretraining with other programming language corpus is not transferable. (see below for quote from Nvidia paper) A lot of high quality Verilog is locked in licensed, close source IP blocks covered by NDAs. HDLBits problems are a toy level complexity circuits suitable for Verilog 101 course material. I would set a benchmark for serious HDL design LLM at reaching ability to implement AXI bus components with specified by user functionality, e.g. AXI4 Slave (address, data…

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VerilogEval: Evaluating Large Language Models for Verilog Code Generation · HackerPapers discussions

VerilogEval: Evaluating Large Language Models for Verilog Code Generation — mentioned by pbazarnik