Short reasons for long vectors in HPC CPUs: a study based on RISC-V · HackerPapers discussions

Short reasons for long vectors in HPC CPUs: a study based on RISC-V — mentioned by camel-cdr

Tue, 10 Dec 2024 10:22:25 GMT

"Short reasons for long vectors in HPC CPUs: a study based on RISC-V": https://arxiv.org/abs/2309.06865 Suggests that VLEN>DLEN can help hide the memory latency. "Instruction Scheduling in the Saturn Vector Unit": https://arxiv.org/html/2412.00997v1 > VII-A Chime Length > The “native” chime length in Saturn, for instructions with no register grouping, is given by the VLEN:DLEN ratio. Increasing the native chime length reduces overall throughput pressure on many components in Saturn, including instruction fetch, load-store queue sizes, issue-queue sizes, and sequencer throughput. > However, a…

Paper and discussion history. A mention is not an endorsement.

Short reasons for long vectors in HPC CPUs: a study based on RISC-V — mentioned by camel-cdr

Sat, 25 May 2024 17:26:27 GMT

> What is the measurable benefit to implementing 128b SVE2 Probably not much, SVE2 has some nicer instructions, but neon already is quite solid. > And implementing 256b SVE has different issues depending on how you do it For in-order, and not very aggressively out-of-order cores having a larger vector length can be very useful to still get a lot of throughput out of your design. It also helps hide memory latency. Here is a paper: https://ar5iv.labs.arxiv.org/html/2309.06865 and presentation: http://riscv.epcc.ed.ac.uk/assets/files/sc23/Short-reasons-f... For aggressively out-of-order cores it…

Paper and discussion history. A mention is not an endorsement.