Chip-Chat: Challenges and Opportunities in Conversational Hardware Design · HackerPapers discussions

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design — HN submission

Sun, 06 Jul 2025 18:51:16 GMT

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design (2023)

2 points; 0 discussion replies on HN. Paper and source history. A submission is not an endorsement.

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design — mentioned by nicklecompte

Sat, 23 Dec 2023 13:11:53 GMT

"It is noteworthy that ChatGPT didn’t design the CPU in its entirety. Yes, NYU researchers used ChatGPT to translate the ‘plain English’ that describes a chip and its capabilities to a Hardware Descriptor Language (HDL) such as Verilog." "It its entirety" is doing a lot of work - I would say ChatGPT didn't design anything, period. I strongly recommend reading the actual chat logs from the data[1]. ChatGPT implemented a very detailed design, and it needed a lot of help to do so. This is still very impressive, but it ultimately reflects GPT-4 being a semi-reliable knowledge base and an…

Paper and discussion history. A mention is not an endorsement.

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design — mentioned by LeafItAlone

Sat, 23 Dec 2023 11:01:18 GMT

It like this is the relevant paper: https://arxiv.org/pdf/2305.13243v1.pdf This is pretty amazing

Paper and discussion history. A mention is not an endorsement.

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design — HN submission

Tue, 20 Jun 2023 17:01:59 GMT

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design

2 points; 1 discussion reply on HN. Paper and source history. A submission is not an endorsement.

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design — mentioned by johndoe0815

Sun, 18 Jun 2023 23:30:00 GMT

Clicking through three levels of links, the non peer-reviewed paper discussed in that article is this one: https://arxiv.org/pdf/2305.13243.pdf Short summary - it still needs a human expert to identify and sort out the plagiarized bullshit generated by ChatGPT and similar LLMs to obtain syntactically and semantically correct Verilog code even for a very simple 8 bit architecture. While this might be a novel way to do design space exploration, it seems to be a pretty frustrating approach to me…

Paper and discussion history. A mention is not an endorsement.