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<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Benchmarking Large Language Models for Automated Verilog RTL Code Generation · HackerPapers discussions</title><link>https://hackerpaper.kaipfister.de/p/2212.11140/</link><description>Collected HN comments and submissions linking this paper.</description><language>en</language><lastBuildDate>Mon, 02 Nov 2026 11:16:22 GMT</lastBuildDate><atom:link href="https://hackerpaper.kaipfister.de/p/2212.11140/feed.xml" rel="self" type="application/rss+xml" /><item><title>Benchmarking Large Language Models for Automated Verilog RTL Code Generation — mentioned by moyix</title><link>https://news.ycombinator.com/item?id=35348498</link><guid isPermaLink="false">urn:hackerpapers:mention:2212.11140:35348498</guid><pubDate>Tue, 28 Mar 2023 21:54:00 GMT</pubDate><description>&lt;p&gt;We found that Codex was pretty bad at Verilog and so we fine-tuned our own models on Verilog code, starting from the SalesForce CodeGen model. The paper will be at DATE: https://arxiv.org/abs/2212.11140 The largest model we trained is here: https://huggingface.co/shailja/fine-tuned-codegen-16B-Verilo...&lt;/p&gt;&lt;p&gt;&lt;a href="https://hackerpaper.kaipfister.de/p/2212.11140/"&gt;Paper and discussion history&lt;/a&gt;. A mention is not an endorsement.&lt;/p&gt;</description><category>cs.PL</category></item></channel></rss>
