arXiv:2211.16212cs.CR
Control-Flow Integrity at RISC: Attacking RISC-V by Jump-Oriented Programming
Early discovery. Linked by one identifiable commenter. This paper is outside the main ranking; a mention is not an endorsement.
Abstract
RISC-V is an open instruction set architecture recently developed for embedded real-time systems. To achieve a lasting security on these systems and design efficient countermeasures, a better understanding of vulnerabilities to novel and potential future attacks is mandatory. This paper demonstrates that RISC-V is sensible to Jump-Oriented Programming, a class of complex code-reuse attacks, able to bypass existing protections. We provide a first analysis of RISC-V systems' attack surface exploitable by such attacks, and show how they can be chained together in order to build a full-fledged attack. We use a conservative hypothesis on exploited registers and instruction patterns, in an approach we called reserved registers. This approach is implemented on a vulnerable RISC-V application, and successfully applied to expose an AES256 secret.
There was a paper on this topic last year (different authors AFAICT): https://arxiv.org/abs/2211.16212 Also an earlier attempt to fix it with a custom RISC-V extension: https://ieeexplore.ieee.org/document/8714980 which was implemented in an FPGA. It seems like the consensus is…
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