Deep Differentiable Logic Gate Networks · HackerPapers discussions

Deep Differentiable Logic Gate Networks — mentioned by thesz

Thu, 27 Nov 2025 22:10:12 GMT

SparseCores appear to be block-sparse as opposed to element-sparse. They use 8- and 16-wide vectors to compute. Here's another inference-efficient architecture where TPUs are useless: https://arxiv.org/pdf/2210.08277 There is no matrix-vector multiplication. Parameters are estimated using Gumbel-Softmax. TPUs are of no use here. Inference is done bit-wise and most efficient inference is done after application of boolean logic simplification algorithms (ABC or mockturtle). In my (not so) humble opinion, TPUs are example case of premature optimization.

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Deep Differentiable Logic Gate Networks — mentioned by calebh

Sat, 22 Nov 2025 15:30:53 GMT

Yes, you can relax logic gates into continuous versions which makes the system differentiable. An AND gate can be constructed with the function x*y and NOT by 1-x (on inputs in the range [0,1]. From there you can construct a NAND gate, which is universal and can be used to construct all other gates. Sigmoid can be used to squash the inputs into [0,1] if necessary. This paper lists out all 16 possible logic gates in Table 1 if you're interested in this sort of thing: https://arxiv.org/abs/2210.08277

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Deep Differentiable Logic Gate Networks — mentioned by andy12_

Thu, 29 May 2025 08:51:46 GMT

I also worked a long time ago in recreating the original Deep Differentiable Logic Network paper [1], so I have a couple of additions to make. > I wanted to see if I could learn the wires in addition to the gates. I still think it’s possible, but it’s something I had to abandon to get the model to converge. Actually, I read some other paper where they also learned the wiring, but they did so by alternating the training of the gates and the wires (in some iterations they learned the wiring while keeping the gates frozen, and in other they learned the gates while keeping the wiring frozen). The…

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Deep Differentiable Logic Gate Networks — mentioned by enricozb

Wed, 28 May 2025 18:01:34 GMT

Differentiable Logic Gate Networks [0] are super interesting. However, I still don't like that the wiring is fixed initially rather than learned. I did some extremely rough research into doing learnable wirings [1], but couldn't get past even learning ~4-bit addition. [0]: https://arxiv.org/abs/2210.08277 [1]: https://ezb.io/thoughts/program_synthesis/boolean_circuits/2...

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Deep Differentiable Logic Gate Networks — mentioned by gwern

Tue, 24 Sep 2024 19:07:57 GMT

The original cited paper https://arxiv.org/abs/2210.08277 "Deep Differentiable Logic Gate Networks" struck me then as very clever, ultra-efficient/small, hardly any inductive bias or prior... But you have to wonder if it's able to scale reasonably well. Differentiating continuous versions of 16 discrete operations in parallel sounds expensive, especially since you presumably need a bunch of them chained in order to approximate a single neural primitive. Even distilling an existing LLM down might be too hard.

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Deep Differentiable Logic Gate Networks — mentioned by pmg

Sun, 17 Dec 2023 03:44:34 GMT

Curious what approach you’re using. I did some work replicating this paper on an arty7 fpga: https://arxiv.org/abs/2210.08277 - any similarities?

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Deep Differentiable Logic Gate Networks — mentioned by dpflan

Fri, 10 Feb 2023 17:41:29 GMT

If you're into logic gates and deep learning: - Deep Differentiable Logic Gate Networks (https://arxiv.org/pdf/2210.08277.pdf) - Video presentation: Deep Differentiable Logic Gate Networks (https://www.youtube.com/watch?v=VulM891DhI4)

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