<?xml version="1.0" encoding="UTF-8"?>
<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Software Mitigation of RISC-V Spectre Attacks · HackerPapers discussions</title><link>https://hackerpaper.kaipfister.de/p/2206.04507/</link><description>Collected HN comments and submissions linking this paper.</description><language>en</language><lastBuildDate>Mon, 02 Nov 2026 11:16:22 GMT</lastBuildDate><atom:link href="https://hackerpaper.kaipfister.de/p/2206.04507/feed.xml" rel="self" type="application/rss+xml" /><item><title>Software Mitigation of RISC-V Spectre Attacks — mentioned by acdha</title><link>https://news.ycombinator.com/item?id=37064072</link><guid isPermaLink="false">urn:hackerpapers:mention:2206.04507:37064072</guid><pubDate>Wed, 09 Aug 2023 15:21:01 GMT</pubDate><description>&lt;p&gt;I see you’re basically trying to “No True Scotsman” a definition where anything which isn’t RISC-V is too complicated. That’s a shame as the time you’re spending on counterproductive RISC-V advocacy could have been spent learning about this class of attack and how it has nothing to do with the ISA. When a CPU implements speculative execution, this class of attack becomes a concern. If it doesn’t, it’ll be too slow for most applications. Fortunately, the people who are - unlike you - actually helping RISC-V are working on efficient countermeasures: https://arxiv.org/abs/2206.04507&lt;/p&gt;&lt;p&gt;&lt;a href="https://hackerpaper.kaipfister.de/p/2206.04507/"&gt;Paper and discussion history&lt;/a&gt;. A mention is not an endorsement.&lt;/p&gt;</description><category>cs.CR</category></item><item><title>Software Mitigation of RISC-V Spectre Attacks — mentioned by belter</title><link>https://news.ycombinator.com/item?id=31971558</link><guid isPermaLink="false">urn:hackerpapers:mention:2206.04507:31971558</guid><pubDate>Sun, 03 Jul 2022 22:30:54 GMT</pubDate><description>&lt;p&gt;[PDF]: https://arxiv.org/pdf/2206.04507.pdf &amp;quot;...In this paper we focus on the RISC-V cores where speculation is enabled and, as we show, where Spectre attacks are as effective as on x86. Even though RISC-V hardware mitigations were proposed in the past, they have not yet passed the prototype phase. Instead, we propose low-overhead software mitigations for Spectre-BTI, inspired from those used on the x86 architecture, and for Spectre-RSB, to our knowledge the first such mitigation to be proposed. We show that these mitigations work in practice and that they can be integrated in the LLVM…&lt;/p&gt;&lt;p&gt;&lt;a href="https://hackerpaper.kaipfister.de/p/2206.04507/"&gt;Paper and discussion history&lt;/a&gt;. A mention is not an endorsement.&lt;/p&gt;</description><category>cs.CR</category></item><item><title>Software Mitigation of RISC-V Spectre Attacks — HN submission</title><link>https://news.ycombinator.com/item?id=31971557</link><guid isPermaLink="false">urn:hackerpapers:submission:2206.04507:31971557</guid><pubDate>Sun, 03 Jul 2022 22:30:54 GMT</pubDate><description>&lt;p&gt;Software Mitigation of RISC-V Spectre Attacks&lt;/p&gt;&lt;p&gt;&lt;/p&gt;&lt;p&gt;1 point; 2 discussion replies on HN. &lt;a href="https://hackerpaper.kaipfister.de/p/2206.04507/"&gt;Paper and source history&lt;/a&gt;. A submission is not an endorsement.&lt;/p&gt;</description><category>cs.CR</category></item></channel></rss>
