TPP: Transparent Page Placement for CXL-Enabled Tiered-Memory — mentioned by cbsks

Thu, 15 Jun 2023 01:00:57 GMT

Here’s a preprint of the paper: https://arxiv.org/pdf/2206.02878.pdf

Paper and discussion history. A mention is not an endorsement.

TPP: Transparent Page Placement for CXL-Enabled Tiered-Memory — mentioned by pbalcer

Wed, 29 Jun 2022 09:06:34 GMT

There's a significant momentum behind CXL [1]. Samsung already announced a CXL DRAM module [2]. From where I sit, it's all but inevitable that this technology will get broader adoption, at least with large CSPs. Its benefits are just too good to pass up. The extra latency is estimated to be no worse than a NUMA hop [3]. Many companies are already figuring out how to best deal with the more complex memory topologies that CXL will enable [4, 5]. But I'm biased (I work for Intel), so take what I say with a grain of salt. [1] - https://www.computeexpresslink.org/members [2]…

Paper and discussion history. A mention is not an endorsement.

TPP: Transparent Page Placement for CXL-Enabled Tiered-Memory · HackerPapers discussions

TPP: Transparent Page Placement for CXL-Enabled Tiered-Memory — mentioned by cbsks

TPP: Transparent Page Placement for CXL-Enabled Tiered-Memory — mentioned by pbalcer