HackerPapers

arXiv:2203.03341cs.DC

Recovering single precision accuracy from Tensor Cores while surpassing the FP32 theoretical peak performance

Hiroyuki Ootomo, Rio Yokota

Abstract

Tensor Core is a mixed-precision matrix-matrix multiplication unit on NVIDIA GPUs with a theoretical peak performance of more than 300 TFlop/s on Ampere architectures. Tensor Cores were developed in response to the high demand of dense matrix multiplication from machine learning. However, many applications in scientific computing such as preconditioners for iterative solvers and low-precision Fourier transforms can exploit these Tensor Cores. To compute a matrix multiplication on Tensor Cores, we need to convert input matrices to half-precision, which results in loss of accuracy. To avoid this, we can keep the mantissa loss in the conversion using additional half-precision variables and use them for correcting the accuracy of matrix-matrix multiplication. Even with this correction, the use of Tensor Cores yields higher throughput compared to FP32 SIMT Cores. Nevertheless, the correcting capability of this method alone is limited, and the resulting accuracy cannot match that of a matrix multiplication on FP32 SIMT Cores. We address this problem and develop a high accuracy, high performance, and low power consumption matrix-matrix multiplication implementation using Tensor Cores, which exactly matches the accuracy of FP32 SIMT Cores while achieving superior throughput. The implementation is based on NVIDIA's CUTLASS. We found that the key to achieving this accuracy is how to deal with the rounding inside Tensor Cores and underflow probability during the correction computation. Our implementation achieves 51TFlop/s for a limited exponent range using FP16 Tensor Cores and 33TFlop/s for full exponent range of FP32 using TF32 Tensor Cores on NVIDIA A100 GPUs, which outperforms the theoretical FP32 SIMT Core peak performance of 19.5TFlop/s.

arXiv comments
Journal reference
DOI
doi:10.1177/10943420221090256
Subjects
cs.DCDistributed, Parallel, and Cluster Computing

On Hacker News

Linked by 2 identifiable commenters in 2 comments across 2 threads, from Jan 2023 to May 2025.

Comments linking this paper, per year.

Discussed in comments2 threads

    • Not really. That's 15.8 fp16 ops compared to 14.7 fp32 ops (that are actually useful outside AI). It would be interesting to see if you can configure the ANE to recover fp32 precision at lower throughput [1]. [1] https://arxiv.org/abs/2203.03341

      Archit3chView on HNParent context

    • Before I forget, here's the link to the tcFFT paper https://ar5iv.labs.arxiv.org/html/2104.11471v1 And the fp32-gemm-with-tf32 https://arxiv.org/abs/2203.03341

      touisteurView on HNParent context

Submitted to Hacker News

Connected through shared HN threads, not inferred similarity or a recommendation.