Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins · HackerPapers discussionshttps://hackerpaper.kaipfister.de/p/2109.14520/Collected HN comments and submissions linking this paper.enMon, 02 Nov 2026 11:16:22 GMTImproving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins — mentioned by belterhttps://news.ycombinator.com/item?id=28741280urn:hackerpapers:mention:2109.14520:28741280Sun, 03 Oct 2021 23:00:26 GMT<p>https://arxiv.org/pdf/2109.14520.pdf</p><p><a href="https://hackerpaper.kaipfister.de/p/2109.14520/">Paper and discussion history</a>. A mention is not an endorsement.</p>cs.ARImproving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins — HN submissionhttps://news.ycombinator.com/item?id=28741279urn:hackerpapers:submission:2109.14520:28741279Sun, 03 Oct 2021 23:00:26 GMT<p>Improving DRAM Performance, Security, Reliability by Understanding DRAM Timing</p><p></p><p>14 points; 4 discussion replies on HN. <a href="https://hackerpaper.kaipfister.de/p/2109.14520/">Paper and source history</a>. A submission is not an endorsement.</p>cs.AR