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<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Recognition of handwritten MNIST digits on low-memory 2 Kb RAM Arduino board using LogNNet reservoir neural network · HackerPapers discussions</title><link>https://hackerpaper.kaipfister.de/p/2105.02953/</link><description>Collected HN comments and submissions linking this paper.</description><language>en</language><lastBuildDate>Mon, 02 Nov 2026 11:16:22 GMT</lastBuildDate><atom:link href="https://hackerpaper.kaipfister.de/p/2105.02953/feed.xml" rel="self" type="application/rss+xml" /><item><title>Recognition of handwritten MNIST digits on low-memory 2 Kb RAM Arduino board using LogNNet reservoir neural network — mentioned by cpldcpu</title><link>https://news.ycombinator.com/item?id=40196630</link><guid isPermaLink="false">urn:hackerpapers:mention:2105.02953:40196630</guid><pubDate>Mon, 29 Apr 2024 10:31:45 GMT</pubDate><description>&lt;p&gt;On the CH32V003, a load should be two cycles if the code is executed from SRAM, there are additional wait states for load from flash. The V2A does only cache a single 32 bit instruction word, so there is basically no cache. This publication seems to describe more details on the arduino implementation: https://arxiv.org/abs/2105.02953 It appears that the code is even using floats in some implementations, which have to be emulated. So I&amp;#x27;d wager that both on algorithmic level (QAT-NN) and implementation level there are some discrepancies that lead to better performance on the CH32V003.&lt;/p&gt;&lt;p&gt;&lt;a href="https://hackerpaper.kaipfister.de/p/2105.02953/"&gt;Paper and discussion history&lt;/a&gt;. A mention is not an endorsement.&lt;/p&gt;</description><category>cs.LG</category></item></channel></rss>
