A First Look at RISC-V Virtualization from an Embedded Systems Perspective — mentioned by chem83

Tue, 22 Jun 2021 23:19:01 GMT

Do you happen to have a link to this discussion? I couldn't find anything associated with the spec commits on [1]. One of the aspects folks were looking forward to seeing is the specification of the 2-stage IOMMU, which S-mode or other parts of the spec don't address per the lengthy discussion on [2]. Thanks. [1] https://github.com/riscv/riscv-isa-manual/commits/master/src... [2] https://arxiv.org/pdf/2103.14951.pdf

Paper and discussion history. A mention is not an endorsement.

A First Look at RISC-V Virtualization from an Embedded Systems Perspective · HackerPapers discussions

A First Look at RISC-V Virtualization from an Embedded Systems Perspective — mentioned by chem83