Fast Stencil-Code Computation on a Wafer-Scale Processor · HackerPapers discussions

Fast Stencil-Code Computation on a Wafer-Scale Processor — mentioned by tyingq

Thu, 10 Jun 2021 14:36:49 GMT

There's better info here: https://blog.inten.to/hardware-for-deep-learning-part-4-asic... "The instruction set supports operations on INT16, FP16, and FP32 types. Floating-point adds, multiplies, and fused multiply-accumulate (or FMAC, with no rounding of the product prior to the add) can occur in a 4-way SIMD manner for 16-bit operands. The instruction set supports SIMD operations across subtensors of four-dimensional tensors, making use of tensor address generation hardware to efficiently access tensor data in memory." The source appears to be this PDF: https://arxiv.org/pdf/2010.03660.pdf

Paper and discussion history. A mention is not an endorsement.

Fast Stencil-Code Computation on a Wafer-Scale Processor — mentioned by rrss

Thu, 19 Nov 2020 15:55:09 GMT

The corresponding paper is very interesting: https://arxiv.org/pdf/2010.03660.pdf Particularly the SpMV CS-1 code listing on page 5, and this comment (in section VI.B) about accuracy: > The measured normwise relative residuals with mixed and 32-bit are shown in Figure 9. Up to iteration 7 the mixed precision implementation tracks the 32-bit, but then fails to reduce the residual further. With this precision, machine precision is about 10^−3. We have observed this accuracy for very well conditioned systems. Here, the growth of rounding errors during the iterative solve explains the loss of an…

Paper and discussion history. A mention is not an endorsement.

Fast Stencil-Code Computation on a Wafer-Scale Processor — HN submission

Sun, 11 Oct 2020 20:51:39 GMT

Fast Stencil-Code Computation on a Wafer-Scale Processor

1 point; 0 discussion replies on HN. Paper and source history. A submission is not an endorsement.