Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core — mentioned by sanxiyn

Thu, 23 Jul 2020 09:26:14 GMT

Their implementation of time protection is presented here: "Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core". https://arxiv.org/abs/2005.02193 They use cache partitioning, but that's not the whole story. Temporal fence instruction, fence.t, is introduced. In their first try, they cleared L1, TLB, branch history, and flushed pipeline. They discovered this is not enough, and covert timing channel persisted. In their second try, in addition to first try, they cleared cache replacement state, cache arbitration state, and TLB replacement state. This eliminated…

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Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core · HackerPapers discussions

Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core — mentioned by sanxiyn