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<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Exploring the Behavior of Coherent Accelerator Processor Interface (CAPI) on IBM Power8+ Architecture and FlashSystem 900 · HackerPapers discussions</title><link>https://hackerpaper.kaipfister.de/p/1909.07166/</link><description>Collected HN comments and submissions linking this paper.</description><language>en</language><lastBuildDate>Mon, 02 Nov 2026 11:16:22 GMT</lastBuildDate><atom:link href="https://hackerpaper.kaipfister.de/p/1909.07166/feed.xml" rel="self" type="application/rss+xml" /><item><title>Exploring the Behavior of Coherent Accelerator Processor Interface (CAPI) on IBM Power8+ Architecture and FlashSystem 900 — mentioned by snaky</title><link>https://news.ycombinator.com/item?id=22030227</link><guid isPermaLink="false">urn:hackerpapers:mention:1909.07166:22030227</guid><pubDate>Sun, 12 Jan 2020 22:54:11 GMT</pubDate><description>&lt;p&gt;It seems some highest-performant enterprise solutions consider the MS-DOS way as well. &amp;quot;The Coherent Accelerator Processor Interface (CAPI) is a general term for the infrastructure that provides high throughput and low latency path to the flash storage connected to the IBM POWER 8+ System. CAPI accelerator card is attached coherently as a peer to the Power8+ processor. This removes the overhead and complexity of the IO subsystem and allows the accelerator to operate as part of an application. In this paper, we present the results of experiments on IBM FlashSystem900 (FS900) with CAPI…&lt;/p&gt;&lt;p&gt;&lt;a href="https://hackerpaper.kaipfister.de/p/1909.07166/"&gt;Paper and discussion history&lt;/a&gt;. A mention is not an endorsement.&lt;/p&gt;</description><category>cs.DC</category></item></channel></rss>
