PERI: A Posit Enabled RISC-V Core — mentioned by vlmutolo

Sat, 08 Aug 2020 03:48:37 GMT

I was reading through the RISC-V ISA spec―specifically the section on floats―and thought "I wonder if RISC-V and its brand-new ISA are a good time to introduce that 'posit' thing I read about a couple years ago." Then I looked it up, and, of course, a bunch of smart people had arrived at that conclusion before me. Thought it might be worth sharing here. More technical details can be found in the PERI paper [0]. [0]: https://arxiv.org/abs/1908.01466

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PERI: A Posit Enabled RISC-V Core · HackerPapers discussions

PERI: A Posit Enabled RISC-V Core — mentioned by vlmutolo