A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping
Sitansusekhar Roymohapatra, Ganesh R. Gore, Akanksha Yadav, Mahesh B. Patil, Krishnan S. Rengarajan, Subhramanian S. Iyer, Maryam Shojaei Baghini
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Abstract
This article is withdrawn because the co-authors are not in favor of publication.
arXiv comments
This article was uploaded by mistake without taking consent of co-authors including my Ph.D. guide. The co-authors are not in favor of publication of this article in arXiv. Hence I am withdrawing it. This is my mistake and I apologize for this