Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs · HackerPapers discussions

Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs — mentioned by stefanpie

Tue, 02 Jan 2024 20:04:04 GMT

I believe that nextpnr has integrated both a simulated annealing placer and an analytical placer (based on this publication from 2019: https://arxiv.org/abs/1903.10407) (see here for the work the analytical placer is based on: https://ieeexplore.ieee.org/abstract/document/6339278). I think they are also working on electrostatic placement but I'm not sure what the current status of that is.

Paper and discussion history. A mention is not an endorsement.

Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs — mentioned by throwmeawaysoon

Thu, 10 Feb 2022 17:35:44 GMT

this is true in general but 1) vivado webpack edition (ie free) lets you write (and flash) a bitstream for some of the small chips. i know it at least works for the artix-7 family because i'm doing it every day lately 2) for the artix-7 (and some lattice chips) you supposedly can use OSS (https://github.com/SymbiFlow/prjxray). i haven't tried it yet but one problem i can foresee is that the OSS tools won't infer stuff like brams and dsp. in fact the symbiflow people (i think?) explicitly call this out as the part of the project that's a work in progress. some useful links…

Paper and discussion history. A mention is not an endorsement.

Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs — HN submission

Thu, 16 May 2019 18:09:59 GMT

Yosys+nextpnr: OSS Framework from Verilog to Bitstream for Commercial FPGAs

3 points; 0 discussion replies on HN. Paper and source history. A submission is not an endorsement.