uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures ยท HackerPapers discussionshttps://hackerpaper.kaipfister.de/p/1810.04610/Collected HN comments and submissions linking this paper.enMon, 02 Nov 2026 11:16:22 GMTuops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures โ€” mentioned by CalChrishttps://news.ycombinator.com/item?id=19138445urn:hackerpapers:mention:1810.04610:19138445Mon, 11 Feb 2019 21:17:49 GMT<p>There is also uops.info which has a different, more formal characterization of latency: https://arxiv.org/abs/1810.04610</p><p><a href="https://hackerpaper.kaipfister.de/p/1810.04610/">Paper and discussion history</a>. A mention is not an endorsement.</p>cs.PFuops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures โ€” HN submissionhttps://news.ycombinator.com/item?id=18209818urn:hackerpapers:submission:1810.04610:18209818Sat, 13 Oct 2018 20:20:49 GMT<p>Uops.info: Characterizing Latency, Throughput, and Port Usage on Intel</p><p></p><p>31 points; 19 discussion replies on HN. <a href="https://hackerpaper.kaipfister.de/p/1810.04610/">Paper and source history</a>. A submission is not an endorsement.</p>cs.PFuops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures โ€” HN submissionhttps://news.ycombinator.com/item?id=18191597urn:hackerpapers:submission:1810.04610:18191597Thu, 11 Oct 2018 07:39:05 GMT<p>Characterizing Latency, Throughput, and Port Usage of Instns on Intel UArch</p><p></p><p>2 points; 0 discussion replies on HN. <a href="https://hackerpaper.kaipfister.de/p/1810.04610/">Paper and source history</a>. A submission is not an endorsement.</p>cs.PF