<?xml version="1.0" encoding="UTF-8"?>
<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>A 3.8 ps RMS time synchronization implemented in a 20 nm FPGA · HackerPapers discussions</title><link>https://hackerpaper.kaipfister.de/p/1806.03400/</link><description>Collected HN comments and submissions linking this paper.</description><language>en</language><lastBuildDate>Mon, 02 Nov 2026 11:16:22 GMT</lastBuildDate><atom:link href="https://hackerpaper.kaipfister.de/p/1806.03400/feed.xml" rel="self" type="application/rss+xml" /><item><title>A 3.8 ps RMS time synchronization implemented in a 20 nm FPGA — HN submission</title><link>https://news.ycombinator.com/item?id=17293240</link><guid isPermaLink="false">urn:hackerpapers:submission:1806.03400:17293240</guid><pubDate>Tue, 12 Jun 2018 13:55:02 GMT</pubDate><description>&lt;p&gt;A 3.8 ps RMS time synchronization implemented in 20 nm FPGA&lt;/p&gt;&lt;p&gt;&lt;/p&gt;&lt;p&gt;2 points; 0 discussion replies on HN. &lt;a href="https://hackerpaper.kaipfister.de/p/1806.03400/"&gt;Paper and source history&lt;/a&gt;. A submission is not an endorsement.&lt;/p&gt;</description><category>eess.SP</category></item></channel></rss>
