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arXiv:1804.06826cs.DC

Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking

Zhe Jia, Marco Maggioni, Benjamin Staiger, Daniele P. Scarpazza

Abstract

Every year, novel NVIDIA GPU designs are introduced. This rapid architectural and technological progression, coupled with a reluctance by manufacturers to disclose low-level details, makes it difficult for even the most proficient GPU software designers to remain up-to-date with the technological advances at a microarchitectural level. To address this dearth of public, microarchitectural-level information on the novel NVIDIA GPUs, independent researchers have resorted to microbenchmarks-based dissection and discovery. This has led to a prolific line of publications that shed light on instruction encoding, and memory hierarchy's geometry and features at each level. Namely, research that describes the performance and behavior of the Kepler, Maxwell and Pascal architectures. In this technical report, we continue this line of research by presenting the microarchitectural details of the NVIDIA Volta architecture, discovered through microbenchmarks and instruction set disassembly. Additionally, we compare quantitatively our Volta findings against its predecessors, Kepler, Maxwell and Pascal.

arXiv comments
Technical report. First Edition. April 18th, 2018. 66 pages
Journal reference
DOI
Subjects
cs.DCDistributed, Parallel, and Cluster Computing cs.PFPerformance

On Hacker News

Linked by 4 identifiable commenters in 9 comments across 9 threads, from Mar 2019 to Aug 2025. Found in 4 HN submissions from Apr 2018 to Jan 2025. Open submission discussions.

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Discussed in comments9 threads

    • Cool project! How do you think about targeting hardware-specific ISAs directly? There’s an interesting paper from Citadel (https://arxiv.org/pdf/1804.06826) that highlights inefficiencies in nvcc for the Volta architecture. Do you see Luminal’s search-based paradigm eventually…

      aleininView on HNParent context

    • Modern GPU instructions are often VLIW and the compiler has to do a lot to schedule them. For example, Nvidia's Volta (from 2017) uses 128-bit to encode each instruction. According to [1], the 128 bits in a word are used as follows: • at least 91 bits are used to encode the…

      GregarianChildView on HNParent context

  1. AI Flame Graphs 1 comment
    • The issue there is that that info is what Nvidia chooses to port out from the on-chip execution. Most of what we can do for observation is in the kernel driver space and not really on-chip or even low level transit to the chip. One of the other commenters pointed out that you…

      wcunningView on HNParent context

  2. Faster CRC32-C on x86 1 comment
    • There's some very interesting flags at the lowest level of NVidia SASS (machine code) that the PTX compiler adds. https://arxiv.org/pdf/1804.06826.pdf PDF Page 14 (physical page 12) shows that every instruction on NVidia Volta SASS has 4-bits of "Reuse flags", 6-bits of "wait…

      dragontamerView on HNParent context

    • > Do you have a hardcore introduction with even more detail / perhaps even with examples of implementations? Hard to beat the actual technical references when you want something hardcore! The actual CUDA documentation is good…

      dragontamerView on HNParent context

    • > You assume so, for Volta onwards that's not true. https://arxiv.org/pdf/1804.06826.pdf NVidia's SASS on Volta is pretty clearly SIMD-instructions. The PTX "virtual machine assembly" is fully documented. SASS is not documented, but it ain't a secret either. SASS follows closely…

      dragontamerView on HNParent context

  3. Nvidia to Acquire Arm for $40B 1 comment
    • NVidia Volta: https://arxiv.org/pdf/1804.06826.pdf Each machine instruction on NVidia Volta has the following information: * Reuse Flags * Wait Barrier Mask * Read/Write barrier index (6-bit bitmask) * Read Dependency barriers * Stall Cycles (4-bit) * Yield Flag (1-bit software…

      dragontamerView on HNParent context

  4. RISC Is Unscalable 1 comment
    • > Since you mentioned this in the same breath as GPUs, I feel I have to point out that according to some reverse engineering paper, Nvidia's Turing is a VLIW architecture. (I'm talking about the actual hardware here, not PTX.) NVidia Volta / Turing has been reverse engineered…

      dragontamerView on HNParent context

    • > Incidentally PTX is a fiction - more of an IR than something with true throughput and latency numbers. I don't know if anyone programs GPUs directly but that would be interesting. PTX is a fiction, but its very close to the underlying "SASS" assembly language of NVidia GPUs.…

      dragontamerView on HNParent context

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