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<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>NVIDIA Tensor Core Programmability, Performance &amp; Precision · HackerPapers discussions</title><link>https://hackerpaper.kaipfister.de/p/1803.04014/</link><description>Collected HN comments and submissions linking this paper.</description><language>en</language><lastBuildDate>Mon, 02 Nov 2026 11:16:22 GMT</lastBuildDate><atom:link href="https://hackerpaper.kaipfister.de/p/1803.04014/feed.xml" rel="self" type="application/rss+xml" /><item><title>NVIDIA Tensor Core Programmability, Performance &amp; Precision — mentioned by m0zg</title><link>https://news.ycombinator.com/item?id=22246330</link><guid isPermaLink="false">urn:hackerpapers:mention:1803.04014:22246330</guid><pubDate>Wed, 05 Feb 2020 12:57:56 GMT</pubDate><description>&lt;p&gt;https://arxiv.org/pdf/1803.04014.pdf - no matter what they did, they could not go beyond 83TFLOPs in fp16. And that&amp;#x27;s just matrix multiply. Any kind of deep learning workload is going to be a lot slower than that.&lt;/p&gt;&lt;p&gt;&lt;a href="https://hackerpaper.kaipfister.de/p/1803.04014/"&gt;Paper and discussion history&lt;/a&gt;. A mention is not an endorsement.&lt;/p&gt;</description><category>cs.DC</category></item></channel></rss>
