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<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>A Novel Scheduling Framework Leveraging Hardware Cache Partitioning for Cache-Side-Channel Elimination in Clouds · HackerPapers discussions</title><link>https://hackerpaper.kaipfister.de/p/1708.09538/</link><description>Collected HN comments and submissions linking this paper.</description><language>en</language><lastBuildDate>Mon, 02 Nov 2026 11:16:22 GMT</lastBuildDate><atom:link href="https://hackerpaper.kaipfister.de/p/1708.09538/feed.xml" rel="self" type="application/rss+xml" /><item><title>A Novel Scheduling Framework Leveraging Hardware Cache Partitioning for Cache-Side-Channel Elimination in Clouds — mentioned by ithkuil</title><link>https://news.ycombinator.com/item?id=16131458</link><guid isPermaLink="false">urn:hackerpapers:mention:1708.09538:16131458</guid><pubDate>Fri, 12 Jan 2018 08:55:51 GMT</pubDate><description>&lt;p&gt;yes, I meant that to suffer from spectre you just need a shared cache; it&amp;#x27;s not necessary to share address space. It follows from what a cache is. You have a large set of numbers (memory addresses) mapping into a smaller set of numbers (cache lines); my necessity there will be a collision. The mapping is deterministic and you can recover information by looking at these clashes. Some intel high end CPUs have a feature called CAT which was designed to avoid that different workloads interfere too much by stomping on each other&amp;#x27;s cache lines, but I think it&amp;#x27;s meant mostly as a performance feature…&lt;/p&gt;&lt;p&gt;&lt;a href="https://hackerpaper.kaipfister.de/p/1708.09538/"&gt;Paper and discussion history&lt;/a&gt;. A mention is not an endorsement.&lt;/p&gt;</description><category>cs.CR</category></item></channel></rss>
