A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs) · HackerPapers discussionshttps://hackerpaper.kaipfister.de/p/1708.04198/Collected HN comments and submissions linking this paper.enMon, 02 Nov 2026 11:16:22 GMTA scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs) — mentioned by FrereKhanhttps://news.ycombinator.com/item?id=27368383urn:hackerpapers:mention:1708.04198:27368383Wed, 02 Jun 2021 13:24:39 GMT<p>Ultra-low-power neuromorphic processors such as DynapSE[1] have been cross-bar free for several years now, making them a perfect fit for sparse networks (both weight- and activity-sparsity). [1] https://arxiv.org/abs/1708.04198</p><p><a href="https://hackerpaper.kaipfister.de/p/1708.04198/">Paper and discussion history</a>. A mention is not an endorsement.</p>cs.AR