Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility — mentioned by namibj

Sun, 27 Nov 2022 12:24:29 GMT

> For better or for worse, modern CPU design is about doing things thread-unsafe by default. If the programmer recognizes a problem may occur, it is the responsibility of the programmer to put the memory barriers in the right place. This so much. I truly wish RISC-V had decided on the weak memory model (WMM)[0] that allowed load-value speculation in the absence of explicit `Reconcile` fences between dependent loads (i.e., when first loading an address from memory and then loading a value from that address, it can load an old value that was stored after the value's address was stored to…

Paper and discussion history. A mention is not an endorsement.

Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility — mentioned by bshanks

Thu, 02 Nov 2017 18:28:26 GMT

I wonder how the memory model in https://people.mpi-sws.org/~dreyer/papers/promising/paper.pd... compares to the WMM and WMM-S memory models given in https://arxiv.org/pdf/1707.05923.pdf ; and if there are other research memory models out there that should also be considered?

Paper and discussion history. A mention is not an endorsement.

Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility · HackerPapers discussions

Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility — mentioned by namibj

Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility — mentioned by bshanks