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<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Accurate, Large Minibatch SGD: Training ImageNet in 1 Hour · HackerPapers discussions</title><link>https://hackerpaper.kaipfister.de/p/1706.02677/</link><description>Collected HN comments and submissions linking this paper.</description><language>en</language><lastBuildDate>Mon, 02 Nov 2026 11:16:22 GMT</lastBuildDate><atom:link href="https://hackerpaper.kaipfister.de/p/1706.02677/feed.xml" rel="self" type="application/rss+xml" /><item><title>Accurate, Large Minibatch SGD: Training ImageNet in 1 Hour — mentioned by neilmovva</title><link>https://news.ycombinator.com/item?id=16362616</link><guid isPermaLink="false">urn:hackerpapers:mention:1706.02677:16362616</guid><pubDate>Mon, 12 Feb 2018 21:49:38 GMT</pubDate><description>&lt;p&gt;It matters when defining parallel work distribution. Unless memory bandwidth is homogeneous across the whole board (i.e. each TPU on a board gets 600 GB/s to its peers), we can&amp;#x27;t do model parallelism across ASICs efficiently, and must fall back to data parallelism. Which is fine, until you run into limits on maximum batchsize (e.g. up to 8192, as FAIR was able to manage [1] with some tweaks to SGD). [1] https://arxiv.org/abs/1706.02677&lt;/p&gt;&lt;p&gt;&lt;a href="https://hackerpaper.kaipfister.de/p/1706.02677/"&gt;Paper and discussion history&lt;/a&gt;. A mention is not an endorsement.&lt;/p&gt;</description><category>cs.CV</category></item></channel></rss>
