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arXiv:1703.07706cs.CR

Ozone: Efficient Execution with Zero Timing Leakage for Modern Microarchitectures

Zelalem Birhanu Aweke, Todd Austin

Early discovery. Linked by one identifiable commenter. This paper is outside the main ranking; a mention is not an endorsement.

Abstract

Time variation during program execution can leak sensitive information. Time variations due to program control flow and hardware resource contention have been used to steal encryption keys in cipher implementations such as AES and RSA. A number of approaches to mitigate timing-based side-channel attacks have been proposed including cache partitioning, control-flow obfuscation and injecting timing noise into the outputs of code. While these techniques make timing-based side-channel attacks more difficult, they do not eliminate the risks. Prior techniques are either too specific or too expensive, and all leave remnants of the original timing side channel for later attackers to attempt to exploit. In this work, we show that the state-of-the-art techniques in timing side-channel protection, which limit timing leakage but do not eliminate it, still have significant vulnerabilities to timing-based side-channel attacks. To provide a means for total protection from timing-based side-channel attacks, we develop Ozone, the first zero timing leakage execution resource for a modern microarchitecture. Code in Ozone execute under a special hardware thread that gains exclusive access to a single core's resources for a fixed (and limited) number of cycles during which it cannot be interrupted. Memory access under Ozone thread execution is limited to a fixed size uncached scratchpad memory, and all Ozone threads begin execution with a known fixed microarchitectural state. We evaluate Ozone using a number of security sensitive kernels that have previously been targets of timing side-channel attacks, and show that Ozone eliminates timing leakage with minimal performance overhead.

arXiv comments
Journal reference
DOI
Subjects
cs.CRCryptography and Security cs.ARHardware Architecture

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Linked by 1 identifiable commenter in 3 comments across 3 threads, from Jul 2018 to Oct 2018.

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Discussed in comments3 threads

  1. About the ZipCPU 1 comment
    • I considered doing it just to run security-critical apps on CPU's like CHERI that I couldn't get in ASIC form: https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ Slow, $2000-a-unit hardware might be worth it if it makes your OS close to unhackable. I'd just have to make…

      nickpsecurityView on HNParent context

    • Interesting. I'm mostly not tracking these since there is a ton of CompSci work post-Meltdown/Spectre. I do periodically look for things that try to stop many attacks at once. Here's two I found that were interesting with one in hardware and one for clouds on top of a verified…

      nickpsecurityView on HNParent context

    • Language-based Information Flow Security (2003) http://www.cs.cornell.edu/andru/papers/jsac/sm-jsac03.pdf Note: This is a great overview with plenty of terms you can use to find modern work. It's branching out in all these areas. Key words to use include "non-interference"…

      nickpsecurityView on HNParent context

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