Using System Hyper Pipelining (SHP) to Improve the Performance of a Coarse-Grained Reconfigurable Architecture (CGRA) Mapped on an FPGA — mentioned by sitkack

Wed, 08 Jan 2020 05:52:10 GMT

It sounds like they just went around the room and asked some folks to list off some systems. I don't think a terrible amount of thought was put into this. I'd add the Tandem NonStop to my personal list. I don't know why I overlooked the LGP-30 [1], I'll have to find a schematic. 113 vacuum tubes is really impressive, I wonder if there is any overlap with this design and System Hyper Pipelining [2]. Do you know of other architectures that use time multiplexing to reduce part count? What bit serial computers do you like? Ahh, it is the Story of Mel computer, awesome. [1]…

Paper and discussion history. A mention is not an endorsement.

Using System Hyper Pipelining (SHP) to Improve the Performance of a Coarse-Grained Reconfigurable Architecture (CGRA) Mapped on an FPGA — mentioned by sitkack

Mon, 01 May 2017 03:45:11 GMT

System Hyper Pipelining [1] can solve lots of problems with logic density, area reuse and having the right balance between operations on data and moving data around. [1] https://arxiv.org/abs/1508.07139

Paper and discussion history. A mention is not an endorsement.

Using System Hyper Pipelining (SHP) to Improve the Performance of a Coarse-Grained Reconfigurable Architecture (CGRA) Mapped on an FPGA · HackerPapers discussions

Using System Hyper Pipelining (SHP) to Improve the Performance of a Coarse-Grained Reconfigurable Architecture (CGRA) Mapped on an FPGA — mentioned by sitkack

Using System Hyper Pipelining (SHP) to Improve the Performance of a Coarse-Grained Reconfigurable Architecture (CGRA) Mapped on an FPGA — mentioned by sitkack