The Cost of Address Translation · HackerPapers discussions

The Cost of Address Translation — HN submission

Wed, 21 Oct 2020 20:43:10 GMT

The asymptotic cost of address translation on memory access time

1 point; 0 discussion replies on HN. Paper and source history. A submission is not an endorsement.

The Cost of Address Translation — mentioned by adrianN

Tue, 29 May 2018 10:15:50 GMT

You just need to use a machine model that takes into account the cost of address translation and the TLB. Check out https://arxiv.org/abs/1212.0703 for some introduction to the topic.

Paper and discussion history. A mention is not an endorsement.

The Cost of Address Translation — mentioned by corysama

Mon, 30 Jan 2017 22:27:10 GMT

A paper came up on HN recently that showed that C arrays could have log(N) behavior for individual accesses if you antagonized the TLB cache hard enough. It got more discussion on Reddit than HN though. https://arxiv.org/abs/1212.0703 https://news.ycombinator.com/item?id=12385458 https://www.reddit.com/r/programming/comments/509qhd/randoml...

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The Cost of Address Translation — mentioned by Tojot

Mon, 29 Aug 2016 21:22:53 GMT

In response to "The Myth of RAM" https://news.ycombinator.com/item?id=12383012 It so happens that a large part of my PhD was on this very subject. The result I've got N log(N), this is more visible when you get to larger RAM (I had 0,5 TB RAM at the time). We have an empirical result, a justification and a rigorous predictive model. The reason has to do with hashing, but a different type: TLB. Feel free to take a look at a free copy at http://arxiv.org/abs/1212.0703 where we establish the VAT cost model.

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The Cost of Address Translation — HN submission

Mon, 29 Aug 2016 21:22:37 GMT

Accessing RAM sometimes costs extra log(N)

50 points; 3 discussion replies on HN. Paper and source history. A submission is not an endorsement.

The Cost of Address Translation — mentioned by matt_d

Tue, 29 Dec 2015 19:40:33 GMT

I realize that this is another topic, although in a somewhat similar context, so I thought I may just ask: Have there been any advances in reducing the page walk latency? I'm thinking of the virtual address translation costs having impact on the run times of common algorithms, e.g., as demonstrated in the following work by Jurkiewicz & Mehlhorn: http://arxiv.org/abs/1212.0703 The recent research I'm aware of is, e.g., Generalized Large-page Utilization Enhancements (GLUE) mechanism, proposed in "Large Pages and Lightweight Memory Management in Virtualized Environments" (from this year's…

Paper and discussion history. A mention is not an endorsement.